1. Field of the Invention
The present invention relates to a digital control method PLL (Phase Locked Loop) for generating an output signal in phase synchronization with an externally inputted reference signal and pulse generating apparatus suitable for use in the implementation of this PLL method.
2. Description of the Related Art
Conventional, well known PLL apparatus employing digital control are, for example, equipped with an oscillating circuit whereby a reference clock is counted and a pulse signal is outputted when this count value reaches a value corresponding to that for externally inputted binary digital data. An oscillating signal which is phase synchronized with the reference signal is then outputted from this oscillating circuit.
With this kind of PLL apparatus, the period for the reference signal is coded so that phase synchronization can be achieved between the output signal from the oscillating circuit and the reference signal. The oscillating signal can then be generated at the same period as the reference signal directly after activation of the oscillating circuit by storing this value in the oscillating circuit. After this, the phase difference between the output signal and the reference signal is detected and the digital data inputted to the oscillating circuit is controlled so that this phase difference becomes a predetermined value (for example, zero).
In another kind of PLL apparatus which is also well known, the oscillating signal from the oscillating circuit has a period divided by 1/n by a period divider so that an oscillating signal which has a period which is 1/n of the reference signal period Ti may be outputted from the oscillator. The phase difference between this period-divided signal and the reference signal is then detected by a phase comparator and the binary digital data inputted to the oscillating circuit is then generated so that this phase difference becomes zero.
However, with PLL apparatus in which a reference signal from an oscillating circuit is period divided to generate a signal, if there is an error with regards to the period To of the oscillating signal from the oscillating circuit, this error is made n-times larger by the period divider. It is therefore necessary to keep the error for the period To of the oscillating signal down to at least less than To/n, so that the stage is not reached where phase comparisons cannot be carried out due to the phase differences being too large. In order to achieve this, it is necessary for the time resolution Td for the circuit to be less than To/n.
In order to increase the time resolution of the circuit, i.e. keep the errors in the reference signal low, the frequency of the reference clock inputted to the oscillating circuit has to be raised or it is necessary to employ high-speed digital circuits in the internal circuitry. However, the structure of the oscillating circuit becomes more complicated as the time resolution Td is raised and the equipment also becomes more expensive.
Also, in the prior art it has only been possible to input reference clocks of about a few hundred MHz at most into the oscillating circuit due to the fact that fixed oscillators have been used to generate the reference clocks inputted to the oscillating circuits. This means that it has only been possible to set up time resolutions which have been of about a few nanoseconds at the most as the time resolution Td for the oscillating circuits, with the raising of this time resolution proving to be a limiting factor. This means that controllable output frequency for this kind of conventional digital type PLL apparatus is restricted to a maximum of about 10 MHz.
However, with this kind of PLL apparatus, even if the time resolution Td for the oscillating circuit is larger than To/n, it is still necessary to synchronize the oscillating signal with the reference signal. In order to achieve this, as shown in FIG. 4, a selector 72 which selects one of either the upper M-bit data exclusive of the lower N-bit data of binary digital data generated in response to the phase difference between an oscillating signal and a reference signal or data which expresses the value for the upper M-bit data with "1" added on and inputs this data to an oscillating circuit 70, a counter 74 which counts the oscillating signal outputted from the oscillating circuit 70 and a comparator 76 which compares the count value for the counter 74 and the lower N-bits of the binary digital data and then outputs a select signal to the selector 72 in response to this result are set up. In this way, the average period Toa of the oscillating signal within one period of the reference signal is made to be 1/n of the period Ti of the reference signal. In this way, the phase of the period divided signal and the reference signal are made to coincide (Japanese Patent Laid-open Publication Hei. 4-13719).
For example, in the case where the period which is the period Ti for the reference signal by 1/n, i.e., the period Ti/n is divided by the time resolution Td of the oscillating circuit 70 to become the value Ti/(n.times.Td), hereinafter denoted as Ti/(n. Td), so that this is then expressed in binary as [1100.101], the upper four bits which fall before the radix point [1100] and this value with one added on [1101] are inputted to the selector 72. The lower three bits which fall after the radix point [101] are then inputted to the comparator 76. In this way, as shown in FIG. 5(b), the data [1101] is inputted to the oscillating circuit for five times until the lower three bits of the count value for the oscillating signal outputted from the counter 74 reaches [101]. The data [1100] is then inputted to the oscillating circuit 70 for three times from the lower three-bit count value reaching [101]until it returns to [000]. In this way, the average value for the eight oscillating signal periods outputted from the oscillating circuit 70 within one period of the reference signal is made to be [1100.101]. Errors in the period divided signal period divided down from the oscillating signal are therefore reduced and the phases of the period divided signal and the reference signal are made to coincide.
However, in the case where the selector 72 is changed over by the counter 74 and the comparator 76, as shown in FIG. 5(b), the portion for the initial number of times corresponding to the lower N-bits of the binary digital data is longer than the period Ti of the reference signal multiplied by 1/n i.e. longer than Ti/n. After this, the oscillating signal is outputted at a period which is shorter than the period Ti/n. This means that there are a large number of errors at the times other than when the periods for n oscillating signals coincide with one period of the reference signal.
Accordingly, for example, this kind of PLL apparatus is used in digital communications to generate a clock signal multiplied from an externally inputted low frequency clock signal. If this clock signal is the used as a timing signal for latching communications data, it will not be possible to latch the communications data correctly.
However, rather than changing over the selector by making the counter value from the counter 74 consecutively larger or smaller than a value expressing the lower N-bits of the binary digital data, as shown in FIG. 5(a), the percentage of the time for which the selector 72 is changed over to a particular position within one period of the reference signal can be made to correspond to the lower N-bit data so that the selector 72 is frequently changed over.
Also, if a pulse generating apparatus capable of generating a pulse signal for changing over the selector 72 at a frequency corresponding to the lower N-bits of the binary digital data is used in place of the comparator 76, as shown in FIG. 5(a), the periods for the oscillating signal outputted within one period of the reference signal can be made to approach an ideal characteristic.
This kind of variable pulse generating apparatus where the pulse signal generating frequency corresponds to binary digital data is disclosed in the kind of changeover control area put forward in the prior art in papers by Mitsubishi Electric Co., Ltd., whereby an apparatus generates a signal in a pattern which corresponds to binary digital data in synchronization with an externally inputted clock signal.
However, with this pulse generating apparatus for the prior art, various circuits for use in pulse signal generation pattern control such as memory for storing pulse signal generation patterns corresponding to externally inputted binary digital data, read out circuitry for storing pulse signal generation patterns corresponding to binary digital data read out from this memory in read-out registers, etc. and pulse generating circuitry for generating pulse signals corresponding to the pattern data stored in registers, etc. in synchronization with externally inputted clock signals are required. Also, the number of items of pattern data and the capacity required to store one item of pattern data increases as the number of bits of binary digital data increase.
The pulse generating apparatus for the prior art such as the changeover control area disclosed in Japanese Patent Laid-Open Publication Hei. 4-113719 is appropriate when generating pulse signals with patterns corresponding to binary digital data of about three bits. However, if the number of bits in the binary digital data is large, the structure of the apparatus becomes complicated, the amount of memory for storing the generation patterns becomes large and the apparatus becomes inappropriate in practical terms.